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description the m pd75116(a) is one of the 4-bit single-chip micro- computer 75x series. the m pd75116(a) is a product with the extended rom capacity of the m pd75108(a). in addition of high-speed operations, it can manipulate data in units of 1, 4 and 8 bits. in particular, the i/o operation of the m pd75116 have been improved by a wide variety of bit control instructions. the m pd75116 is provided with interface inputs/outputs with peripheral circuits having different power voltages, and analog inputs and suitable for controlling automobile electrical equipment, etc. for the m pd75116(a), an on-chip pin-compatible one-time prom product ( m pd75p116) is separately available for system development evaluation. functions are described in detail in the following users manual, which should be read when carrying out design work. m pd751 series users manual: iem-992 features higher reliability than m pd75116 architecture "75x" equivalent to 8-bit microcomputer minimum instruction execution time (high-speed operation): 0.95 m s (when operated at 4.19 mhz and 5 v) instruction execution variable function: 0.95 m s/1.91 m s/ 15.3 m s (when operated at 4.19 mhz) many input/output ports: 58 3-channel on-chip 8-bit timers 8-bit on-chip serial interface multi-interruptible vector interrupt function applications automobile electrical equipment, etc. data sheet m pd75112(a), 75116(a) 4-bit single chip-microcomputer ?nec corporation 1990 qualty grade special special special special package 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 20 mm) 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 20 mm) ordering code m pd75112cw(a)- m pd75112gf(a)- -3be m pd75116cw(a)- m pd75116gf(a)- -3be remarks : is a rom code number. please refer to "quality grade on nec semicon- ductor devices" (document number iei-1209) pub- lished by nec corporation to know the specifica- tion of quality grade on the devices and its recom- mended applications. unless there are any particular functional differences, the m pd75116(a) is described in this document as a representative product. the information in this document is subject to change without notice. the mark h shows major revised points. document no. ic-2811a (o. d. no. ic-8261a) date published march 1994 p printed in japan
2 m pd75112(a), 75116(a) item no. of basic instruction min. instruction execution time on-chip memory general register accumulator input/output port timer/counter serial interface vector interrupt test input standby operating temperature range operating voltage others package description 43 0.95 m s/1.91 m s/15.3 m s (when operated at 4.19 mhz), switchable at 3 levels 12160 8 ( m pd75112(a)), 16256 8 ( m pd75116(a)) 512 4 4 bits 8 4 banks (memory mapping) three accumulated in compliance with controlled date lengths 1-bit accumulator (cy), 4-bit accumulator (a), 8-bit accumulator (xa) 58 in total cmos input pin : 10 cmos input/output pin (led direct drive enable) : 32 intermediate withstand voltage n-ch open drain : 12 input/output pin (bit-wise pull-up resistor inscorporation possible) comparator input pin (4-bit accuracy) : 4 8-bit timer/event counter 2 8-bit basic interval timer (applicable to watchdog timer) 8-bits first lsb/first msb switchable two transfer modes (transmit and receiver/receive dedicated mode) external : 3, internal : 4 external : 2 stop/halt mode -40 to +85 c 2.7 to 6.0 v on-chip power-on reset circuit (mask option) on-chip bit contol memory (bit sequential buffer) 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 20 mm) defferences between m pd75112(a), 75116(a) and m pd75112, 75116 item quality grade electrical specifications direct led drive outline of functions rom ram absolute maximum ratings dc characteristics m pd75112(a), 75116(a) special different high-level output current and low-level output current different low-level output voltage not possible product name m pd75112, 75116 standard possible
3 m pd75112(a), 75116(a) contents 1. pin configuration (top view)............................................................................................... 4 2. block diagram......................................................................................................................... 6 3. pin functions......................................................................................................................... 7 3.1 port pins...................................................................................................................................................... 7 3.2 non-port pins............................................................................................................................................... 8 3.3 pin input/output circuits............................................................................................................................ 9 3.4 recommended connection of unused pins............................................................................................. 10 3.5 caution relating to use of p00/int4 pin and reset pin........................................................................ 10 4. memory configuration............................................................................................................. 11 5. peripheral hardware functions.............................................................................................. 14 5.1 digital input/output port......................................................................................................................... 14 5.2 clock generator......................................................................................................................................... 14 5.3 clock output circuit.................................................................................................................................. 16 5.4 basic interval timer.................................................................................................................................... 16 5.5 timer/event counter................................................................................................................................. 17 5.6 serial interface............................................................................................................................................ 19 5.7 programmable threshold port (analog input port)............................................................................... 21 5.8 bit sequential buffer................................................................................................................................... 22 5.9 power-on flag (mask option).................................................................................................................... 22 6. interrupt functions.................................................................................................................. 23 7. standby functions ............................................................................................................... 25 8. reset functions..................................................................................................................... 26 9. instruction set....................................................................................................................... 29 10. mask option selection.......................................................................................................... 37 11. electrical specifications........................................................................................................ 38 12. package information ............................................................................................................ 48 13. recommended soldering conditions ................................................................................. 51 appendix a. diffeences between m pd751 (a) series products and related prom products.............................................................................. 52 appendix b. development tools ............................................................................................ 53 appendix c. related documentations ................................................................................... 54
4 m pd75112(a), 75116(a) 1. pin configuration (top view) 64-pin plastic shrink dip (750 mil) 1 p13/int3 2 p12/int2 3 p11/int1 4 p10/int0 5 pth03 6 pth02 7 pth01 8 pth00 9 ti0 10 ti1 11 p23 12 p22/pcl 13 p21/pto1 14 p20/pto0 15 p03/si 16 p02/so 17 p01/sck 18 p00/int4 19 p123 20 p122 21 p121 22 p120 23 p133 24 p132 25 p131 26 p130 27 p143 28 p142 29 p141 30 p140 31 nc 32 v dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss p90 p91 p92 p93 p80 p81 p82 p83 p70 p71 p72 p73 p60 p61 p62 p63 x1 x2 reset p50 p51 p52 p53 p40 p41 p42 p43 p30 p31 p32 p33 m pd75112cw(a)- m pd75116cw(a)-
5 m pd75112(a), 75116(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p131 p132 p133 p120 p121 p122 p123 p00/int4 p02/so p01/sck p03/si p20/pto0 p21/pto1 p22/pcl p23 t11 x2 x1 p41 p40 p53 p52 p51 p50 reset p63 p62 p61 p60 p73 p72 p71 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 p42 p43 p30 p31 p32 p33 v dd nc p140 p141 p142 p143 p130 p81 p80 p93 p92 p91 p90 v ss p13/int3 p12/int2 p11/int1 p10/int0 pth03 pth02 17 18 19 p70 p83 p82 t10 pth00 pth01 35 34 33 64-pin plastic qfp (14 20 mm) m pd75112gf(a)- -3be m pd75116gf(a)- -3be pin name p00-p03 : port0 sck : serial clock p10-p13 : port1 so : serial output p20-p23 : port2 si : serial input p30-p33 : port3 pto0, pto1 : programmable timer output p40-p43 : port4 pcl : programmable clock p50-p53 : port5 pth00-pth03 : programmable threshold input p60-p63 : port6 int0, int1, int4 : external vectored interrupt input p70-p73 : port7 int2, int3 : external test input p80-p83 : port8 ti0, ti1 : timer input p90-p93 : port9 x1, x2 : clock oscillation p120-p123 : port12 reset : reset p130-p133 : port13 nc : no connection p140-p143 : port14 v dd : positive power supply v ss : ground h
6 m pd75112(a), 75116(a) 2. block diagram rom program memory 12160 8 bits ( pd75112(a)) 16256 8 bits ( pd75116(a)) m p00-p03 p10-p13 port0 port1 4 p20-p23 4 p30-p33 4 p40-p43 4 p50-p53 4 p60-p63 4 p70-p73 4 p80-p83 4 p90-p93 4 p120-p123 4 p130-p133 4 p140-p143 4 4 bit seq. buffer(16) port2 port4 port3 port5 port6 port7 port8 port9 port12 port13 port14 general reg. bank sp (8) cy alu ram data memory 512 4 bit decode and control timer/event counter # 0 timer/event counter # 1 serial interface clock output control clock divider clock generator stand by control cpu clock pcl/p22 f x /2 x1 x2 reset v ss v dd basic interval timer intbt ti0 pto0/p20 ti1 pto1/p21 si/p03 si/p02 int0/p10 int1/p11 int2/p12 int3/p13 int4/p00 4 pth00-pth03 sck/p01 intt0 intt1 intsio interrupt control programmable threshold port # 0 program counter (14) m n f
7 m pd75112(a), 75116(a) 3. pin functions 3.1 port pins pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 function 4-bit input port (port0) 4-bit input port (port1) 4-bit input/output port (port2) programmable 4-bit input/output port (port3) bit-wise input/output setting enable 4-bit input/output port (port4) 4-bit input/output port (port5) programmable 4-bit input/output port (port6) bit-wise input/output setting enable 4-bit input/output port (port7) 4-bit input/output port (port8) 4-bit input/output port (port9) n-ch open drain 4-bit input/ output port (port12) bit-wise pull-up resistor incorporation enable (mask option) 2 v withstand for open drain n-ch open drain 4-bit input/ output port (port13) bit-wise pull-up resistor incorporation enable (mask option) 12 v withstand for open drain n-ch open drain 4-bit input/output port (port14) bit-wise pull-up resistor incorporation enable (mask option) 12 v withstand for open drain i/o circuit type *1 b f e b b e e e e e e e e m m m input/ output input input/output input/output input input input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output 8-bit i/o l l l l l l l l at reset input input input input input input input input input input input *2 input *2 input *2 * 1 : circles indicate schmitt trigger inputs. 2 : high impedance for open drain high level for on-chip pull-up resistors dual function pin int4 sck so si int0 int1 int2 int3 pto0 pto1 pcl
8 m pd75112(a), 75116(a) pth00 to pth03 ti0 ti1 pto0 pto1 sck so si int4 int0 int1 int2 int3 pcl x1, x2 reset nc *2 v dd v ss 3.2 non-port pins dual function pin p20 p21 p01 p02 p03 p00 p10 p11 p12 p13 p22 i/o circuit type *1 n b e f e b b b b e b at reset input input input input input input input input input/output input input input/output input/output input/output input input input input input/output input function threshold voltage ariable 4-bit analogy input port. external event pulse input for the timer/event counter or edge detect vector interrupt input. 1-bit input enable. timer/event counter output. serial clock input/output. serial data output. serial data input. edge detect vector interrupt input (for detecting both rising and falling edges). edge detect vector interrupt input (detected edge selectable). edge detect testable input (for rising edge detection). clock output. crystal/ceramic connect pin (system clock oscillation). in case with the external clock, input a signal to x1 and the antiphase to x2. system reset input (low level active). no connection positive power supply. gnd potential. *1 : circles indicate schmitt trigger inputs. 2 : when the pwb is shared with the m pd75p116, connect the nc pin to v dd directly.
9 m pd75112(a), 75116(a) type f input/output circuit consisting of a type d push-pull output and a type b schmitt-triggered input. type m pull-up register (mask option) n-ch (+6 v withstand) middle-high voltage input buffer (+6 v withstand) type n comparator v ref (threshold voltage) 3.3 pin input/output circuits m pd75116(a) pin input/output crcuit are shown in sche- matic form. figure 3-1 pin input/output circuits in/out data output disable type d type b p-ch v dd in n-ch in + in p-ch v dd out n-ch data output disable in/out data output disable type d type a in/out v dd data output disable type a cmos specified input buffer type b schmitt triggered-input with hysteresis characteristics type d push-pull output which can be set at output high impedance (with both p-ch an n-ch set to off) type e input/output circuit consisting of a type d push-pull output and a type a input buffer
10 m pd75112(a), 75116(a) 3.5 caution relating to use of p00/int4 pin and reset pin in addition to the functions described in sections 3.1 and 3.2, the p00/int4 pin and the reset pin have the function to set the ic test mode for testing the m pd75116(a) internal operations. when a voltage larger than v dd is applied to one of these two pins, the test mode is set. thus, if noise exceeding v dd is applied even during normal opera- tions, the test mode is set and normal operations may be discontinued. for example, if a cable from the p00/int4 or reset pin is too long, inter-wiring noise may be applied to the pin, the pin voltage may become larger than v dd , causing malfunctioning. thus, carry out wiring to minimize inter-wiring noise. if the noise cannot be suppressed completely, carry out the following countermeasure against noise using an externally mounted component. o connect a diode with low v f (max 0.3 v)between v dd s diode with low v f o connect acapacitor between v dd s 3.4 recommended connection of unused pins pin pth00 to pth03 ti0 ti1 p00 p01 to p03 p10 to p13 p20 to p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 reset nc *1 : only when a power-on reset generator is built in by mask option, connect t v dd . 2 : when the pwb is shared with the m pd75p116, connect the nc pin to v dd directly. recommended connecting method connect to v ss or v dd connect to v ss connect to v ss or v dd connect to v ss input state : connect to v ss or v dd output state : leave open connect to v dd *1 leave open or connect to v dd *2 v dd v dd p00/int4, reset v dd v dd p00/int4, reset
11 m pd75112(a), 75116(a) 4. memory configuration program memory (rom) 12160 8 bits (0000h to 2f7fh): m pd75112(a) 16256 8 bits (0000h to 3f7fh): m pd75116(a) 0000h to 0001h: vector table for writing the program start address by reset 0002h to 000bh: vector table for writing the program start address by interrupt remarks : in all other cases, the program can be branched by the br pcde and br pcxa 0020h to 007fh: table area to be referred to by the geti instruction data memory data area 512 4 bits (000h to 1ffh) peripheral hardware area 128 4 bits (f80h to fffh) instructions to an address with only the lower 8 bits of pc changed. figure 4-1 program memory map ( m pd75112(a)) address ? ? ? mbe rbe mbe rbe mbe mbe rbe mbe rbe mbe rbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0fffh 76 0 internal reset start address internal reset start address (low-order 8 bits) int0/int1 start address (high-order 6 bits) int0/int1 start address (low-order 8 bits) (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 6 bits) intt1 start address geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br !addr instruction branch address call !addr instruction subroutin entry address brcb !caddr instruction branch address ? (high-order 6 bits) rbe intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) ? ? ? ? ? ? 2000h 1fffh 2f7fh 0800h 1000h brcb !caddr instruction branch address br $addr instruction relative branch address (-15 to +16) branch address subroutine entry address by geti instruction
12 m pd75112(a), 75116(a) figure 4-2 program memory map ( m pd75116(a)) address remarks : in all other cases, the program can be branched by the br pcde and br pcxa instructions to an address with only the lower 8 bits of pc changed. ? ? ? mbe rbe mbe rbe mbe mbe rbe mbe rbe mbe rbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0fffh 76 0 internal reset start address internal reset start address (low-order 8 bits) int0/int1 start address (high-order 6 bits) int0/int1 start address (low-order 8 bits) (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (high-order 6 bits) intt1 start address (high-order 6 bits) intt1 start address geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br !addr instruction branch address call !addr instruction subroutin entry address brcb !caddr instrucion branch address ? (high-order 6 bits) rbe intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) ? ? ? ? ? ? ? ? 2000h 1fffh 3000h 2fffh 3f7fh 0800h 1000h brcb !caddr instruction branch address br $addr instruction relative branch address (-15 to ? +2 to +16) brcb !caddr instrucion branch address branch address subroutine entry address by geti instruction
13 m pd75112(a), 75116(a) figure 4-3 data memory map memory bank data memory 000h 01fh 0ffh 100h 1ffh f80h fffh bank 0 bank 1 bank 15 256 4 128 4 256 4 (32 4) general regoster area stack area data area static ram (512 4) peripheral hardware area not incorporated
14 m pd75112(a), 75116(a) table 5-1 functions of digital ports remarks share the pins with si, so, sck and int0 to 4. port 2 shares the pin with pto0, pto1 and pcl. on-chip pull-up registers can be specified bit-wise by mask option. 5. peripheral hardware functions 5.1 digital input/output port the digital input/output port has the following tree types. cmos input (port0, 1) : 8 cmos input/output (port 2 to port 9) : 32 n-ch open-drain input/output (port 12 to port 14): 12 total 52 functions 4-bit input 4-bit input/ output 4-bit input/ output (n-ch open- drain, 12 v withstand voltage) port (code) port0 port1 port3 port6 port2 port4 port5 port7 port8 port9 port12 port13 port14 operations and features read or test always enable irrespectively of the operating mode of dual-function pins. can be set bit-wise to the input or output mode. can be set in 4-bit units to the input or output mode. ports 4 and 5, 6 and 7, 8 and 9 can form pairs and data can be input/output in 8-bit units. can be set in 4-bit units the input or output mode. ports 12 and 13 can form a pair and data can be input/output in 8- bit units. 5.2 clock generator the clock generator is a circuit which supplies the cpu and peripheral hardware with various clocks and con- trols the cpu operating mode. the instruction execution time can be changed. 0.95 m s/1.91 m s/15.3 m s (at 4.19 mhz operation)
15 m pd75112(a), 75116(a) figure 5-1 block diagram of clock generator basic interval timer (bt) clock generator timer/event counter serial interface clock output circuit s rq 1/4 s stop f/f halt f/f q r 1/2 1/16 1/8 to 1/4096 pcc fx fxx or pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 crear stop * halt * 4 ? ? ? ? ? ? f ?cpu ?clock output circuit inter- nal bus system clock oscillator oscillation stop frequency divider selec- tor frequency divider wait release signal from bt res(internal reset) signal standby release signal from the interrupt control circuit remarks 1 :f xx =crystal/ceramic oscillator frequency. 2 :f x =external clock frequency. 3 : f =cpu clock 4 : * indicates instruction execution. 5 : pcc (processor clock control register) 6 : 1 clock cycle (t cy) of f is 1 michine cycle of the instruc- tion. for t cy , see the ac characteristics in the 11."elec- trical specifications" . h
16 m pd75112(a), 75116(a) 5.4 basic interval timer the basic interval timer has the following functions; interval timer operation to generate reference time interrupts watchdog timer application to detect program overrun wait time selection and count when the standby mode is released count content read 5.3 clock output circuit the clock output circuit is a circuit to generate clock pulses from the p22/pcl pin. it is used to supply the peripheral lsis with clock pulses. clock output (pcl): f , 524 khz, 262 khz (at 4.19 mhz operation) the clock output cicuit configuration is shown as the following. figure 5-2 clock output circuit configuration port2.2 clom3 clom1 clom0 fxx/2 clom 0 4 3 fxx/2 4 f from the clock generator selector internal bus p22 output latch port 2 input/ output mode specification bit pmgb bit 2 p22/pcl output buffer
17 m pd75112(a), 75116(a) figure 5-3 basic interval timer configuration remark : * indicates instruction execution. 5.5 timer/event counter the m pd75116(a) has a two-channel on-chip timer/ event counters. channels 0 and 1 of the timer/event counter have the same configuration and functions. they differ only in the selectable count pulse (cp) and the function of supplying clocks to the serial interface. the timer/event counter has the following functions: programmable interval timer operation output of square wave having any selected fre- quency to pton pin event counter operation use of tin pin as an external interrupt input pin output of tin pin input divided by n to pton pin (frequency divider operation) serial shift clock supply to the serial interface circuit (channel 0 only) count status read function btm3 btm2 btm1 btm0 btm from the clock generator * set1 fxx/2 4 3 9 fxx/2 7 fxx/2 5 fxx/2 mpx 12 3 8 irqbt bt internal bus basic interval timer (8-bit frequency divider) clear clear wait release signal when the standby mode is released bt interrupt request flag vector interrupt request signal set
18 m pd75112(a), 75116(a) figure 5-4 block diagram of timer/event counter (n=0, 1) tmn7 tmn6 tmn5 tmn4 tmn3 tmn2 tmn1 tmn0 tmn set 1 *1 ? ? ? ? ? *2 tin 8 8 8 tmodn match tofn tn cp res clear tmn1 tmn0 irqtn clear signal irqtn p2n/pton to serial interface *3 inttn toen ton port2.n tout f/f 8 8 tin mpx input buffer from clock generator timer operation start internal bus modulo register (8) comparator (8) count register (8) to selector to enable flag p2n output latch port2 input/ output mode pgmb bit 2 output buffer edge detector set signal *1: set1: instruction execution 2: refer to figure 5-1 3: only channel 0 of the time/event counter can output a signal to the serial interface
19 m pd75112(a), 75116(a) 5.6 serial interface the m pd75116(a) incorporates the clock synchronous 8-bit serial interface. the serial interface has the follow- ing two modes. operation stop mode 3-wire serial i/o mode (msb/lsb top switching possible) connection with the m pd75116(a) and the 75x series, 78k series and various i/o devices is possible in the 3- wire serial i/o mode.
20 m pd75112(a), 75116(a) *: set1: instruction execution figure 5-5 block diagram of serial interface siom7 siom6 siom5 siom4 siom3 siom2 siom1 siom0 siom set1 * 8 8 clear r s q over flow serial clock counter (3) serial start 8 sio0 sio7 sio p03/si p02/so p01/sck mpx fxx/2 4 10 fxx/2 tof 0 f internal bus shift register (8) (from timer channel 0) intsio irqsio set signal irqsio clear signal ? ?
21 m pd75112(a), 75116(a) 5.7 programmablethreshold port (analog input port) the m pd75116(a) is equipped with 4-bit analog input pins (pth00 to pth03) capable of changing the thresh- old voltage. these pins are configured as shown in figure 5-6. sixteen threshold voltage (v ref ) values (v dd -v dd ) are available and analog signals can be directly input. the analog input port can also be used as a digital signal input port by selecting v dd for v ref . 16 0.5 16 15.5 16 7.5 figure 5-6 block diagram of programmable threshold port + pth00 + pth01 + pth02 + pth03 1 2 r 4 1 2 r mpx v dd v ref r r pthm7 pth0 pthm6 pthm5 pthm4 pthm3 pthm2 pthm1 pthm0 pthm 8 operation stop program- mable threshold port input latch (4) input buffer inter- nal bus
22 m pd75112(a), 75116(a) 5.8 bit sequential buffer ... 16 bit the bit sequential buffer is a special data memory for bit control. since this buffer can easily operate bits by sequentially changing address and bit specifications, it can be conveniently be used for bit-wise processing of data having long bit lengths. figure 5-7 bit sequential buffer format l = f l = c l = b l = 8 l = 7 l = 4 l = 3 decs l incs l l = 0 bsb0 bsb1 bsb2 bsb3 32 1 fc3h 0 32 1 fc2h 0 32 1 fc1h 0 32 1 fc0h 0 address bit symbol l register remarks : in pmen. @l addressing, the specified bit moves in accordance with the l register. 5.9 power-on flag (mask option) the power-on flag (ponf) is only set (1) when the power-on reset circuit is activated and the power-on reset signal is generated (see figure 8-1 ). ponf is mapped on bit 0 at address fd1h of the data memory space and is manipulated by a bit manipula- tion instruction however, it cannot be set(1) by the set1 instruction.
23 m pd75112(a), 75116(a) 6. interrupt functions there are seven types of interrupt sources for the m pd75116(a) to allow multi-interruption with priority. the m pd75116(a) is also provided with two types of edge detection testable inputs. the m pd75116 interrupt control circuit has the follow- ing functions; hardware controlled vector interrupt function which enables to control by the interrupt enable flag (ie ) and the interrupt master enable flag (ime) whether an interrupt should be enabled. interrupt start address can be set freely. multiple interrupt function which enables to specify priority by the interrupt priority select register (ips). interrupt request flag (irq ) test function (inter- rupt generation can be checked by the software). standby mode release (the interrupt to be released can be selected by the interrupt enable flag).
24 m pd75112(a), 75116(a) figure 6-1 block diagram of interrupt control circuit irqbt 2 irq4 irq0 irq1 irqsio irqt0 irqt1 irq2 irq3 2 9 4 2 i s t i p s (ime) im1 im0 int bt int4 /p00 int0 /p10 int1 /p11 int2 /p12 intsio intt0 intt1 int3 /p13 internal bus interrupt enable flag (ie ) decoder priority control circuit vector table address generator standby release signal interrupt request flag edge detection circuit edge detection circuit edge detection circuit edge detection circuit edge detection circuit
25 m pd75112(a), 75116(a) stop mode stop instruction clock oscillation stop operation stop operation enabled only when external sck input and to0 clock are set for serial clocks (when timer/event counter 0 is set to external ti0 input) is selected operation enabled only when tin pin input is specified for the count clock operation stop operation stop set instruction clock generator basic interval timer serial interface timer/event counter clock output circuit cpu release signal 7. stanby functions two types of standby modes (stop and halt modes) are available for the m pd75116(a) to decrease power consumption during standby for program. table 7-1 operation statuses in standby mode halt mode halt instruction only cpu clock f stop operation (irqbt set at reference time intervals) operation enabled when aclock other than f is specified for the serial clock operation enabled clock other than cpu clock f enabled for output operation stop operation status interrupt request signal enabled by interrupt enable flag or reset input
26 m pd75112(a), 75116(a) 8. reset functions the reset signal (res) generator is configured as shown in figure 8-1. figure 8-1 reset signal generator *: ponf setting (1) by set1 instruction is not possible. swa swb reset power-on reset circuit mask option power-on flag(ponf) bit control instruction execution * internal reset signal (res) inter- nal bus
27 m pd75112(a), 75116(a) the power-on reset circuit generates the internal reset signal by rising of supply voltage. this pulse is used in the three ways according to the specification of mask option of swa and swb shown in figure 8-1 (refer to "10. mask option selection" ). reset operations are shown in figures 8-2 and 8-3. figure 8-2 reset operation by power-on reset *: the wait time does not include a time from the generation of res signal to the start of oscillation. each hardware status after reset operation is shown in table 8-1. figure 8-3 reset operation by reset input halt mode 0v supply voltage internal reset signal (res) wait * (approx. 31.3 ms:4.19 mhz) internal reset operation operating mode halt mode operation or standby mode wait * (approx. 31.3 ms:4.19 mhz) internal reset operation operating mode reset input
28 m pd75112(a), 75116(a) table 8-1 hardware statuses after reset *1: power-on reset ................... 1 reset input in operation ... undefined 2: data at addresses 0f8h to 0fdh of the data memory becomes undefined due to reset input. pws basic interval timer timer/ event counter (n = 0, 1) serial interface reset input in power-on reset or operation same as left undefined 0 0 same as left undefined undefined undefined 0, 0 undefined 0 0 ffh 0 0, 0 undefined 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 undefined 0 1 or undefined *2 0 clock generator, clock output circuit interrupt digital port analog port reset input in standby mode lower 6 bits of address 0000h of the program memory are set to pc 13 to pc 8 and the content of address 0001h is set to pc 7 to pc 0 . hold 0 0 bits 6 and 7 of address 0000h of the program memory are set to rbe and mbe, respectively. undefined hold *1 hold 0, 0 undefined 0 0 ffh 0 0, 0 hold 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 undefined 0 hold 0 hardware program counter (pc) carry flag (cy) skip flag (sk0 to sk2) interrupt status flag (ist0, 1) bank enable flags (mbe, rbe) stack pointer (sp) data memory (ram) general registers (x, a, h, l, d, e, b, c) bank select registers (mbs, rbs) counter (bt) mode register (btm) counter (tn) modulo register (tmodn) mode register (tmn) toen, tofn shift register (sio) mode register (siom) processor clock control register (pcc) clock output mode register (clom) interrupt request flag (irq ) interrupt enable flag (ie ) priority select resister (ips) int0, 1 mode resisters (im0, im1) output buffer output latch input/output mode registers (pmga, pmgb, pmgc) pth00 to pth03 input latches mode register (pthm) power-on flag (ponf) bit sequential buffers (bsb0 to bsb3)
29 m pd75112(a), 75116(a) * : in the case of 8-bit data processing, only even address can be described for mem. description method x, a, b, c, d, e, h, l x, b, c, d, e, h, l xa, bc, de, hl bc, de, hl bc, de xa, bc, de, hl, xa, bc, de, hl bc, de, hl, xa, bc, de, hl hl, hl+, hl-, de, dl de, dl 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label * 2-bit immediate data or label fb0h to fbfh and ff0h to fffh immediate data or labels fc0h to fffh immediate data or labels m pd75112(a) 0000h to 2f7fh immediate data or labels m pd75116(a) 0000h to 3f7fh immediate data or labels 12-bit immediate data or label 11-bit immediate data or label 20h to 7fh immediate data (bit = 0) or labels port0 to port9, port12 to port14 iebt, iesio, iet0, iet1, ie0 to ie4 rb0 to rb3 mb0, mb1, mb15 identifier reg reg1 rp rp1 rp2 rp rp1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr portn ie rbn mbn 9. instruction set (1) operand identifier and description method in the operand column of each instruction, describe the corresponding operand in accordance with the de- scription method for the operand identifier of the in- struction (refer to the " ra75x assembler package user's manual language volume" (eeu-730) for details). if more than one description method is available, select one of them. capital alphabetic letters, plus and minus signs are key words. describe them as they are. in the case of immediate data, describe appropriate numeric values or labels. symbols of various registers and flags can be de- scribed as labels instead of mem, fmem, pmem, bit, etc. (refer to the " m pd751 series users manual (iem- 922) " for details). labels which can be described are limited for fmem and pmem.
30 m pd75112(a), 75116(a) (2) legend in the description of operations a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : extended register pair (xa) bc : extended register pair (bc) de : extended register pair (de) hl : extended register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 9, 12 to 14) ime : interrupt mask enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register . : address and bit division ( ) : content addressed by h : hexadecimal data
31 m pd75112(a), 75116(a) mb=mbe mbs (mbs=0, 1, 15) mb=0 mbe=0 : mb=0 (00h-7fh) mb=15 (80h-ffh) mbe=1 : mb=mbs (mbs=0, 1, 15) mb=15, fmem=fb0h-fbfh, ff0h=fffh mb=15, pmem=fc0h-fffh addr=0000h-2f7fh ( m pd75112(a)) =0000h-3f7fh ( m pd75116(a)) addr=(current pc) -15 to (current pc) +16 caddr=0000h-0fffh (pc 13 , pc 12 =00b : m pd75112(a), 116(a)) or =1000h-1fffh (pc 13 , pc 12 =01b : m pd75112(a), 116(a)) or =2000h-2f7fh (pc 13 , pc 12 =10b : m pd75112(a)) or =2000h-2fffh (pc 13 , pc 12 =10b : m pd75116(a)) or =3000h-3f7fh (pc 13 , pc 12 =11b : m pd75116(a)) faddr=0000h-07ffh taddr=0020h-007fh (3) description of symbols in the addressing area column remarks 1 : mb indicates an accessible memory bank. 2 : in *2 , mb = 0 irrespectively of mbe and mbs. 3 : in *4 and *5 , mb = 15 irrespectively of mbe and mbs. 4 : *6 to *10 indicate addressable areas. (4) description of machine cycle column s indicates the number of machine cycles required for the instruction having skip function to execute skip operation. the value of s varies as follows: when no skip ............................................. s = 0 when 1-byte or 2-byte instruction is skipped ................................................. s = 1 when 3-byte instruction (br !addr, call !addr instructions) is skipped ............................. s = 2 note : geti instruction is skipped in one-ma- chine cycle. one machine cycle is equal to one cycle (=t cy )of cpu clock. three values are available for the one machine cycle by pcc setting. *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 data memory addressing program memory addressing
32 m pd75112(a), 75116(a) instructions mnemonic transfer table reference bit transfer mov xch movt mov1 machine cycle 1 2 2 2 2 1 2+s 2+s 1 2 1 2 2 2 2 2 2 2 2 2 1 2+s 2+s 1 2 2 2 1 2 3 3 2 2 2 2 2 2 no. of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 2 2 operand a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp' reg1, a rp'1 xa a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl a, mem xa, mem a, reg1 xa, rp' xa, @pcde xa, @pcxa cy, fmem. bit cy, pmem. @l cy, @h+mem. bit fmem. bit, cy pmem. @l, cy @h+mem. bit, cy skip condition stack a stack a stack b l=0 l=fh l=0 l=fh addressing area *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *1 *1 *2 *1 *3 *3 *4 *5 *1 *4 *5 *1 operation a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (hl), then l ? l+1 a ? (hl), then l ? l-1 a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp' reg1 ? a rp'1 ? xa a ? (hl) a ? (hl), then l ? l+1 a ? (hl), then l ? l-1 a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp' xa ?( pc 13-8 +de) rom xa ?( pc 13-8 +xa) rom cy ? (fmem.bit) cy ? (pmem 7-2 +l 3-2 .bit(l 1-0 )) cy ? (h+mem 3-0 .bit) (fmem.bit) ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? cy (h+mem 3-0 .bit) ? cy
33 m pd75112(a), 75116(a) operation a ? a+n4 xa ? xa+n8 a ? a + (hl) xa ? xa+rp' rp'1 ? rp'1+xa a, cy ? a+(hl)+cy xa, cy ? xa+rp'+cy rp'1, cy ? rp'1+xa+cy a ? a - (hl) xa ? xa-rp' rp'1 ? rp'1-xa a, cy ? a-(hl)-cy xa, cy ? xa-rp'-cy rp'1, cy ? rp'1-xa-cy a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a " n4 a ? a " (hl) xa ? xa " rp' rp'1 ? rp'1 " xa cy ? a 0 , a 3 ? cy, a n-1 ? an a ? a reg ? reg+1 rp1 ? rp1+1 (hl) ? (hl)+1 (mem) ? (mem)+1 reg ? reg-1 rp' ? rp'-1 skip if reg=n4 skip if (hl)=n4 skip if a=(hl) instructions mnemonic arithmetic accumulator operation increase/ decrease compare adds addc subs subc and or xor rorc not incs decs ske operand a, #n4 xa, #n8 a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a a reg rp1 @hl mem reg rp' reg, #n4 @hl, #n4 a, @hl no. of bytes 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 machine cycle 1+s 2+s 1+s 2+s 2+s 1 2 2 1+s 2+s 2+s 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+s 1+s 2+s 2+s 1+s 2+s 2+s 2+s 1+s skip condition carry carry carry carry carry borrow borrow borrow reg=0 rp1=00h (hl)=0 (mem)=0 reg=fh rp'=ffh reg=n4 (hl)=n4 a=(hl) *1 *1 *1 *1 *1 *1 *1 *1 *3 *1 *1 addressing area
34 m pd75112(a), 75116(a) instructions mnemonic compare carry flag operation ske set1 clr1 skt not1 operand xa, @hl a, reg xa, rp' cy cy cy cy addressing area *1 no. of bytes 2 2 2 1 1 1 1 machine cycle 2+s 2+s 2+s 1 1 1+s 1 operation skip if xa=(hl) skip if a=reg skip if xa=rp' cy ? 1 cy ? 0 skip if cy=1 cy ? cy skip condition xa=(hl) a=reg xa=rp' cy=1
35 m pd75112(a), 75116(a) instructions mnemonic memory bit manipulation branch set1 clr1 skt skf sktclr and1 or1 xor1 br brcb br operand mem. bit fmem. bit pmem. @l @h+mem. bit mem. bit fmem. bit pmem. @l @h+mem. bit mem. bit fmem. bit pmem. @l @h+mem. bit mem. bit fmem. bit pmem. @l @h+mem. bit fmem. bit pmem. @l @h+mem. bit cy, fmem. bit cy, pmem. @l cy, @h+mem. bit cy, fmem. bit cy, pmem. @l cy, @h+mem. bit cy, fmem. bit cy, pmem. @l cy, @h+mem. bit addr !addr $addr !caddr pcde pcxa no. of bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 2 2 2 machine cycle 2 2 2 2 2 2 2 2 2+s 2+s 2+s 2+s 2+s 2+s 2+s 2+s 2+s 2+s 2+s 2 2 2 2 2 2 2 2 2 3 2 2 3 3 operation (mem.bit) ? 1 (fmem.bit) ? 1 (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? 1 (h+mem 3-0 .bit) ? 1 (mem.bit) ? 0 (fmem.bit) ? 0 (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? 0 (h+mem 3-0 .bit) ? 0 skip if (mem.bit)=1 skip if (fmem.bit)=1 skip if (pmem 7-2 +l 3-2 .bit(l 1-0 )) = 1 skip if (h+mem 3-0 .bit)=1 skip if (mem.bit)=0 skip if (fmem.bit)=0 skip if (pmem 7-2 +l 3-2 .bit(l 1-0 ))=0 skip if (h+mem 3-0 .bit)=0 skip if (fmem.bit)=1 and clear skip if (pmem 7-2 +l 3-2 .bit(l 1-0 )) =1 and clear skip if (h+mem 3-0 .bit)=1 and clear cy ? cy (fmem.bit) cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) cy ? cy (h+mem 3-0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) cy ? cy (h+mem 3-0 .bit) cy ? cy " (fmem.bit) cy ? cy " (pmem 7-2 +l 3-2 .bit(l 1-0 )) cy ? cy " (h+mem 3-0 .bit) pc 13-0 ? addr (most appropriate instruction is selected by assembler from among br !addr, brcb !caddr and br $addr) pc 13-0 ? addr pc 13-0 ? addr pc 13-0 ? pc 13, 12 +caddr 11-0 pc 13-0 ? pc 13-8 +de pc 13-0 ? pc 13-8 +xa addressing area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *7 *8 skip condition (mem.bit)=1 (fmem.bit)=1 (pmem.@l)=1 (@h+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@l)=0 (@h+mem.bit)=0 (fmem.bit)=1 (pmem.@l)=1 (@h+mem.bit)=1
36 m pd75112(a), 75116(a) instructions mnemonic subroutine stack control interrupt control input/output cpu control special call callf ret rets reti push pop ei di in *1 out *1 halt stop nop sel geti *2 operand !addr !faddr rp bs rp bs ie ie a, portn xa, portn portn, a portn, xa rbn mbn taddr skip condition unconditional depends on the instruction referred to. * 1: mbe=0 or 1 and mbs=15 must be set for execution of in/out instruction. 2: tbr and tcall instructions are assembler pseudo-instructions for geti instruction table definition. no. of bytes 3 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 machine cycle 3 2 3 3+s 3 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 operation (sp-4)(sp-1)(sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, pc 13, 12 pc 13-0 ? addr, sp ? sp-4 (sp-4)(sp-1)(sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, pc 13, 12 pc 13-0 ?00, faddr, sp ? sp-4 mbe, rbe, pc 13, 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4 mbe, rbe, pc 13, 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4, then skip unconditionally pc 13, 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 (sp-1)(sp-2) ? rp, sp ? sp-2 (sp-1) ? mbs, (sp-2) ? rbs, sp ? sp-2 rp ? (sp-1)(sp), sp ? sp-2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 ime (ips.3) ? 1 ie ? 1 ime (ips.3) ? 0 ie ?0 a ? portn (n=0-9, 12-14) xa ? portn+1, portn (n=4, 6, 8, 12) portn ? 4 (n=2-9, 12-14) portn+1, portn ? xa (n=4, 6, 8, 12) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation rbs ? n(n=0-3) mbs ? n (n=0, 1, 15) tbr instruction pc 13-0 ? (taddr) 4-0 +(taddr+1) tcall instruction (sp-4)(sp-1)(sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, pc 13, 12 pc 13-0 ? (taddr) 5-0 +(taddr+1) sp ? sp-4 when not tbr and tcall instructions, (taddr) and (taddr+1) instructions are executed. , addressing area *6 *9 *10
37 m pd75112(a), 75116(a) 10. mask option selection the following mask options are available for the m pd75116(a). whether or not they should be incorporated can be selected. (1) pins pin p120 to p123 p130 to p133 p140 to p143 mask option bit-wise pull-up resistor incorporation enable (2) power-on reset circuit and power-on flag (ponf) one of the following three settings can be selected. mask option specification power-on reset circuit incorporated not incorporated not incorporated switch selection (see figure 8-1 ) swa on on off swb on off off h internal reset signal (res) generated automatically not generated automatically power-on flag (ponf) incorporated incorporated not incorporated
38 m pd75112(a), 75116(a) test conditions except for ports 12 to 14 ports 12 to 14 1 pin all pins 1 pin total current of ports 0, 2 to 4, 12 to 14 *1 : when applying a voltage larger than 10 v to ports 12, 13 and 14 each, set the power impedance (pull-up resistor) to 50 k w or more. 2 : calculate each effective value using the following expres- sion: [effective value]=[peak value] ? duty note: product quality may suffer if the absolute maxi- mum rating is exceeded for even a single pa- rameter or even momentarily. that is, the ab- solute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 11. electrical specifications absolute maximum ratings (ta = 25 c) unit v v v v v ma ma ma ma ma ma ma ma ma ma c c symbol v dd v i1 v i2 *1 v o i oh i ol *2 t opt t stg on-chip pull-up resistor open drain peak value effective value peak value effective value peak value effective value peak value effective value peak value effective value ratings C0.3 to +7.0 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to +13 C0.3 to v dd +0.3 C10 C5 C30 C15 10 5 50 25 50 25 C40 to +85 C65 to +150 parameter power supply voltage input voltage output voltage output current high output current low operation temperature storage temperature
39 m pd75112(a), 75116(a) test conditions min. *2 4.5 4.5 2.7 max. 6.0 6.0 6.0 6.0 unit v v v v *1 : except system clock oscillator, programmable threshold port and power-on reset circuit 2 : operating voltage range depends on the cycle time. see the ac characteristics . 3 : whether or not it should be incorporated can be selected by mask options. see the power-on reset circuit characteristics (mask option) . h operating voltage (ta = C40 to +85 c) parameter cpu *1 programmable threshold port (comparator input) power-on reset circuit *3 other hardware *1
40 m pd75112(a), 75116(a) oscillate characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) x1 x2 oscillator ceramic oscillation crystal oscillator external clock max. 5.0 *3 5.0 *3 5.0 *3 250 typ. 4.19 min. 2.0 4 2.0 10 30 2.0 100 test condition v dd = oscillation voltage range oscillation voltage range min. v dd = 4.5 to 6.0 v recommended constant parameter oscillator frequency (f xx ) *1 oscillation stabilizing time *2 oscillator frequency (f xx ) *1 oscillation stabilizing time *2 x1 input frequency (f x ) *1 x1 input high and low level widths (t xh , t xl ) unit mhz ms mhz ms ms mhz ns m pd74hcu04 x1 x2 c2 c1 x1 x2 c2 c1 *1 : oscillator frequency and x1 input frequency indicate only characteristics of the oscillator. refer to ac characteristics for the instruction execution time. 2 : the oscillation stabilizing time is necessary for oscillation to stabilize after v dd reaches oscillation voltage range min. or the stop mode is released. 3 : when the oscillator frequency is 4.19 mhz < f xx 5.0 mhz, pcc=0011 should not be selected as instruction execution time. if pcc=0011 is selected, 1 machine cycle becomes less than 0.95 m s, with the result that the specified min. value of 0.95 m s cannot be observed. h note: when using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a vary- ing high current. the potential of the oscillator capacitor ground should be the same as v ss . do not ground wiring to a ground pattern in which a high current flows. do not fetch a signal from the oscillator. h
41 m pd75112(a), 75116(a) symbol v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh v ol i lih1 i lih2 i lih3 i lil1 i lil2 i loh1 i loh2 i lol r l i dd1 i dd2 i dd3 test conditions except for ports listed below ports 0, 1, ti0, 1, reset ports 12 to 14 x1, x2 except for ports listed below ports 0, 1, ti0, 1, reset x1, x2 v dd = 4.5 to 6.0 v, i oh = C1 ma i oh = C100 m a v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0v, i ol = 1.6 ma i ol = 400 m a v in = v dd v in = 12 v v in = 0 v v out = v dd v out = 12 v v out = 0 v ports 12 to 14 4.19 mhz crystal oscillation c1 = c2 = 22 pf stop mode, v dd = 3 v 10% on-chip pull-upresistor open drain ports 0, 2 to 9, i ol = 5 ma ports 12 to 14, i ol = 5 ma except for ports listed below x1, x2 ports 12 to 14 (for open drain) except for x1, x2 x1, x2 except for ports listed below ports 12 to 14 (for open drain) v dd =5 v 10% v dd =5 v 10% *2 v dd =3 v 10% *3 halt mode parameter input voltage high input vltage low output voltage high output voltage low input leakage current high input leakage current low output leakage current high output leakage current low on-chip pull-up resistor supply current *1 dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) *1 : current for the on-chip pull-up resistor, power-on reset circuit (mask option) and comparator circuit is not included. 2 : when operated in the hgh-speed mode with the processor clock v dd =5 v 10% v dd =3 v 10% control resistor (pcc) set tp 0011. 3 : when operated in the low-speed mode with the pcc set to 0000. min. 0.7v dd 0.8v dd 0.7v dd 0.7v dd v dd C0.5 0 0 0 v dd C1.0 v dd C0.5 15 10 typ. 0.25 0.40 40 3 0.55 600 200 0.1 max. v dd v dd v dd 12 v dd 0.3v dd 0.2v dd 0.4 1.0 1.0 0.4 0.5 3 20 20 C3 C20 3 20 C3 70 80 9 1.5 1800 600 10 unit v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a k w k w ma ma m a m a m a
42 m pd75112(a), 75116(a) test conditions f = 1 mhz 0 v for pins except the measured pins symbol c in c out c io parameter input capacitance output capacitance input/output capacitance max. 15 15 15 comparator characteristics (ta = C40 to +85 c, v dd = 4.5 to 6.0 v) parameter comparison accuracy threshold voltage pth input voltage comparator circuit consumption test conditions set pthm7 to "1". symbol v acomp v th v ipth power-on reset circuit characteristics (mask option) (ta = C40 to +85 c) parameter power-on reset operating voltage high power-on reset operating voltage low supply voltage rise time supply voltage off time power-on reset circuit current consumption *2 *1 :2 17 /f xx (31.3 ms when f xx = 4.19mhz) 2 : current flow upon power-on reset or with an on-chip power-on flag note : start the power supply smoothly. t off t r v ddl v dd v ddh capacitance (ta = 25 c, v dd = 0 v) unit mv v v ma max. 100 v dd v dd typ. 1 min. 0 0 symbol v ddh v ddl t r t off i ddpr test conditions v dd = 5 v 10% v dd = 2.5 v min. 4.5 0 10 1 typ. 10 2 max. 6.0 0.2 *1 100 20 unit v v m s s m a m a typ. min. unit pf pf pf
43 m pd75112(a), 75116(a) test conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v parameter cpu clock cycle time * (min. instruction execution time = 1 machine cycle) ti0, ti1 input frquency ti0, ti1 input high and low-level widths sck cycle time sck high and low-level widths si setup time (to sck - ) si hold time (from sck - ) s0 output delay time from sck int0 to int4 high and low-level widths reset low-level sidth ac characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) max. 32 32 1 275 300 1000 typ. symbol t cy f ti t tih, t til t kcy t kh, t kl t sik t ksi t kso t inth, t intl t rsl min. 0.95 3.8 0 0 0.48 1.8 0.8 0.95 3.2 3.8 0.4 t kcy /2-50 1.6 t kcy /2-50 100 400 5 5 input output input output input output input output unit m s m s mhz khz m s m s m s m s m s m s m s ns m s ns ns ns ns ns m s m s
44 m pd75112(a), 75116(a) ac timing test point (except for ports 0, 1, ti0, ti1, x1, x2 and reset) 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points clock timing * : the cycle time of the cpu clock ( f ) is determined by the input frequency of the ceramic crystal oscillator and the setting of the processor clock control register (pcc). the cycle time (t cy ) for v dd is shown below. 40 32 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0.5 supply voltage v dd [v] t cy vs. v dd [v] operation guaranteed range cycle time t cy [ s] m t xl t xh 1/f x v dd ?0.5 0.4 x1 input
45 m pd75112(a), 75116(a) ti0 and ti1 input timing serial transfer timing interrupt input timing t til t tih 1/f ti ti0, ti1 0.8 v dd 0.2 v dd t kl t kh sck si so output data t kcy t sik t kso t ksi 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd input data t intl t inth int0-int4 0.8 v dd 0.2 v dd
46 m pd75112(a), 75116(a) *1 : current for the on-chip pull-up resistor, power-on circuit (mask option) and comparator circuit is not included. 2 : the oscillation stabilizing time is intended to stop the cpu to prevent any unstable operation at the start of oscillation. 3 : depends on the following setting of the basic interval timer mode register (btm). data memory stop mode low supply voltage data retention characteristics (ta = C40 to +85 c) reset input timing symbol v dddr v dddr t srel t wait unit v m a m s ms ms parameter data retention supply voltage data retention supply current *1 release signal set time oscillation stabilization wait time *2 max. 6.0 10 typ. 0.1 2 17 /f x *3 wait time (f xx =4.19 mhz valus in parentheses) 2 20 /f xx (approx. 250 ms) 2 17 /f xx (approx. 31.3 ms) 2 15 /f xx (approx. 7.82 ms) 2 13 /f xx (approx. 1.95 ms) btm3 btm0 0 1 1 1 btm1 0 1 0 1 btm2 0 0 1 1 min. 2.0 0 test conditions v dddr = 2.0 v release by reset release by interrupt request t rsl reset 0.2 v dd
47 m pd75112(a), 75116(a) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request)
48 m pd75112(a), 75116(a) 12. packing information a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
49 m pd75112(a), 75116(a) n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 64-pin plastic qfp (14 20) (unit: mm) h

51 m pd75112(a), 75116(a) recommended condition symbol ir30-00-1 vp15-00-1 ws60-00-1 table 13-2 insertion type soldering conditions m pd75112cw(a)- : 64-pin plastic shrink dip (750 mil) m pd75116cw(a)- : 64-pin plastic shrink dip (750 mil) 13. recommended soldering conditions the m pd75112(a) and 75116(a) should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document surface mount technol- ogy manual (iei-1207) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 13-1 surface mounting type soldering conditions m pd75112gf(a)- -3be : 64-pin plastic qfp (14 20mm) m pd75116gf(a)- -3be : 64-pin plastic qfp (14 20mm) soldering method infrared reflow vps wave soldering pin part heating soldering conditions package peak temperature: 230 c duration: 30 sec. max. (at 210 c above) number of times: once package peak temperature: 215 c duration: 40 sec. max. (at 200 c above) number of times: once solder bath temperature: 260 c max. duration: 10 sec. max. number of times: once preliminary heat temperature: 120 c max. (package surface temperature) pin part temperature: 300 c max. duration: 3 sec. max. (per device side) note: use more than one soldering method should be avoided (except in the case of pin part). soldering method wave soldering (lead part only) pin part heating soldering conditions solder bath temperature: 260 c max. duration: 10 sec. max. pin part temperature: 260 c max. duration: 10 sec. max. note: wave soldering is only for the lead part in order that jet solder can not contact with the chip. h notice a version of this product with improved recommended soldering conditions is available. for details (improvements such as infrared reflow peak temperature extension (235 c, number of times: twice, relaxation of time limit), contact nec sales
52 m pd75112(a), 75116(a) m pd75104(a) 0000h to 0fffh 4096 8 320 4 bank 0: 256 4 bank 1: 64 4 58 cmos input/output: 32 +12 v withstand n-ch voltage open-drain input/output: 12 (pull-up resistor can be on-chip by mask option.) cmos input/output: 10 comparator: 4 can be on-chip by mask option 2.7 to 6.0 v 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 20 mm) item rom configuration rom (bit) ram (bit) instruction set i/o line power-on reset circuit power-on flag supply voltage range package m pd75p108b prom 0000h to 1f7fh 8064 8 cmos input/output: 32 +12 v withstand n-ch open-drain input/ output: 12 each pin can directly drive led: 44 none 2.7 to 6.0 v m pd75106(a) 0000h to 177fh 6016 8 m pd75108(a) 0000h to 1f7fh 8064 8 total input/ output input mask rom differs depending on package special 512 4 bank 0: 256 4 bank 1: 256 4 h 512 4 bank 0: 256 4 bank 1: 256 4 high end high end (only m pd75104(a) does not incorporate br !addr instruction). appendix a. differences between m pd751 (a) series products and related prom prod- ucts m pd75p116 0000h to 3f7fh 16256 8 64-pin plastic shrink dip (750 mil) 64-pin ceramic shrink dip (with window) 64-pin plastic qfp (14 20 mm) 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 20 mm) product name m pd75112(a) 0000h to 2f7fh 12160 8 m pd75116(a) 0000h to 3f7fh 16256 8 pin connection quality grade differs depending on package (with v pp pin) standard 5 v 10%
53 m pd75112(a), 75116(a) appendix b. development tools the following tools are available for the development of systems for which the m pd75116(a) is used. ie-75000-r *1 ie-75001-r ie-75000-r-em *2 ep-75108cw-r ep-75108gf-r ev-9200g64 pg-1500 pa-75p108cw pa-75p116gf ie control program pg-1500 controller ra75x relocatable assembler *1 : maintenance product 2 : not incorporated in the ie-75001-r. 3 : the task swap function, which is provided with ver. 5.00/5.00a, is not available with this software. remarks: for development tools manufactured by a third party, see the 75x series selection guide (if-151) . hardware software 75x series in-circuit emulator emulation board for ie-75000r and ie-75001-r. emulation probe for m pd75112cw(a) and 75116cw(a). emulation probe for m pd75112gf(a) and 75116gf(a). 64-pin conversion socket ev-9200g64 added. prom programmer m pd75p116cw prom programmer adapter connected to pg-1500 m pd75p116gf prom programmer adapter connected to pg-1500 host machine pc-9800 series (ms-dos tm ver. 3.30 to 5.00a *3 ) ibm pc/at tm (pc dos tm ver. 3.1)
54 m pd75112(a), 75116(a) appendix c. related documentations list of device related documentations list of development tools related documentations list of other related documentations document name users manual instruction application table application note 75x series selection guide document number (i) introductory volume (ii) remote control reception volume (iii) bar-code reader volume (iv) ic control for msk transmission/reception volume h iem-1260 iem-1139 iem-1281 iem-1265 iea-1278 if-1027 document name hardware software ie-75000-r/ie-75001-r users manual ie-75000-r-em users manual ep-75108cw-r users manual ep-75108gf-r users manual pg-1500 users manual ra75x assembler package users manual pg-1500 controller users manual document number document name package manual surface mount technology manual quality grade on nec semiconductor devices nec semiconductor device reliability & quality control electrostatic discharge (esd) test semiconductor devices quality guarantee guide microcomputer related products guide other manufactures volume document number operation volume language volume eeu-1416 eeu-1294 eeu-1308 eeu-1318 eeu-1335 eeu-1346 eeu-1343 eeu-1291 iei-1213 iei-1207 iei-1209 mei-1202 note: the contents of the above related documents are subject to change without notice. the lat- est documents should be used for design, etc.
55 m pd75112(a), 75116(a)
m4 92.6 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may ppear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual propety rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equip- ment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporations. m pd75112(a), 75116(a)

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